An increasing concern in advanced digital circuit design is the control of leakage current, especially when the digital logic circuit is in the precharge or standby state, which is often the predominant state in terms of the amount of time that the circuit is in that state compared to states of the circuit. High leakage current can result in the case of battery operated devices, reduced device operating time. Therefore, there is a need for reduced leakage current circuits and method for reducing leakage current in digital CMOS logic circuits.